1. Field of the Invention
The invention generally relates to electronic circuits and particularly to timing recovery circuits.
2. Description of the Related Art
Jitter in a digital communication signal is the variation in time of data (or clock edges) from integer multiples of the bit period unit interval (UI) time. In an ideal signal, the edges occur at exact interval times. In a real signal, there is variation in the edge locations due to various phenomena in the signal generation and transmission system.
The reduction of generated jitter is typically an important aspect of a clock and data recovery circuit. In an analog-type clock recovery circuit, phase noise in a signal generated by a voltage-controlled oscillator (VCO) or in a clock synthesis unit (CSU) can contribute a relatively large component to the generation of random jitter. In a digital-type clock recovery circuit, quantizing noise or quantization noise can provide an additional source of intrinsic jitter. A quantizing jitter component is related to the relatively low-frequency phase tap movements that are used to compensate for the difference in frequency between the frequency of a received data signal and a local clock reference. This is an example of intrinsic jitter, because it exists even when the data signal has no jitter.
Phase-locked loop (PLL) based data clock recovery techniques are commonly used in digital communications systems. The Synchronous Optical Networking (SONET) standard provides an example of a communications standard for communicating digital information over optical fibers. Another example is the Synchronous Digital Hierarchy (SDH) standard.
FIG. 1 illustrates a block diagram for a receiver and a transmitter of a digital communications system. A clock signal (“clock”) 102 is recovered in the receiver 104 from the incoming data signal 106. The recovered clock signal 102 is used for sampling or recovering the data bits in the receiver 104 and can also be provided as an output signal. For example, the recovered clock signal 102 can be used outside the receiver 104 for timing of other networking elements such as a transmitter 110 as shown in FIG. 1. In a SONET system, the use of the recovered clock signal 102 for timing of an outgoing data signal 112 is referred as a loop-timing mode.
Two types of PLL-based clock recovery circuits are typically encountered: analog and digital. In an analog PLL, a frequency of a voltage-controlled oscillator (VCO) is adjusted to track the phase of the incoming data signal 106. Ring oscillators and LC-type oscillators are examples of analog VCOs.
Digital PLLs employ a digital VCO, which is typically implemented as a phase tap movement or selection technique performed on a number of N phases provided by a clock synthesis unit (CSU). Another example of a digital VCO is a multi-tap delay line with the tap movement or selection technique.
The long-term relative frequency offset permissible between two frequency sources is typically specified in parts per million (ppm). For instance, the SONET Minimum Clock (SMC) reference clock signal uses a stability fppm=+/−20 ppm, which corresponds to approximately 50 kHz at OC-48 data rates (2.488 Gb/s). As illustrated in FIG. 2, the frequency offset can typically be viewed in terms of data phase as a linear function of time. If the data phase is expressed in unit intervals (UI), then, as depicted in FIG. 2, the phase slope is equal to the absolute frequency difference, Δf.
Equation 1 expresses the finite phase resolution of a practical digital clock recovery system.ΔφLSB=1/N [UI]  Equation 1
In Equation 1, N is a number of discrete phases generated by the clock synthesis unit (CSU). In one example, a practical range for the number of phases N is between 10 and 32. However, it will be appreciated by the skilled practitioner that a wide range can apply to the number of phases N, and that the number of phases N will be readily determined by one of ordinary skill in the art.
In the illustrated example, the recovered clock signal exhibits an instantaneous timing jitter with a peak-to-peak amplitude equal to the phase step size, ΔφLSB. The instantaneous timing jitter is zero otherwise.
                              J                      GEN            ⁢            _            ⁢            UIpp                          =                ⁢                  Δϕ                      LSB            ,                                                      ⁢                              if            ⁢                                                  ⁢                          f              ppm                                ≠          0                                                  =                    ⁢          0                ,                                    ⁢                              if            ⁢                                                  ⁢                          f              ppm                                =          0                    
The root-mean-square (RMS) jitter is expressed by Equation 2.JGEN—UIrms=JGEN—UIpp/2·√3  Equation 2
The jitter frequency is expressed by Equation 3.Jitter_freq=1/Tj  Equation 3
In Equation 3, Tj is a phase quantizing error period as illustrated in FIG. 2. From FIG. 2, the relationship expressed in Equation 4 can be observed.Tj=ΔφLSB/SLOPE  Equation 4
In Equation 4, SLOPE corresponds to how fast the data phase in unit intervals (UIs) changes over time as expressed in Equation 5.SLOPE=Δf=fppm·DATA_RATE  Equation 5
Combining Equations 1 and 4-6, the jitter frequency can be expressed as:Jitter_freq=fppm·DATA_RATE·N  Equation 6
For the purposes of illustration, examples of SONET requirements for Jitter Generation are listed in Table 1.
TABLE 1SONET requirements for Jitter GenerationMax JitterMax JitterOptical CarrierData RateGenerationGenerationBandwidthLevelMb/sUI pk-pkUI RMSkHzOC-12622.080.10.0112-5000 OC-482488.3200.10.0112-20000
Using the SONET requirements as an example, for a practical range of the number of phases N, such as between 10 and 32, the jitter frequency should be in the SONET frequency specification band. While the use of an even larger number of phases N can provide some benefits, a large number for N also has disadvantages. For example, the number of phases N can be selected to be about 64, which should typically satisfy the maximum SONET jitter generation of 0.01 UIrms requirements with an acceptable margin for error. However, the use of a number of phases N of around 64 disadvantageously significantly complicates the implementation of the digital clock recovery circuit.
FIG. 3 illustrates an example of a conventional implementation for a digital clock recovery system. The conventional digital clock recovery system employs a multi-phase clock synthesis unit (CSU) 302 with N phase taps, a phase detector 304, a digital filter 306, and a phase selection unit 308. The clock signal 310 is recovered, while tracking the data phase in the phase-locked loop is performed with the phase selection unit 308, the phase detector 304 and the digital filter 306. Subject to the low-pass filtering by the digital filter 306, the phase selection unit 308 selects the tap of the CSU 302 closest in phase to the received data 312 to generate the recovered clock signal 310.
Those skilled in the art will recognize that alternative implementations to generate N-phases can be used. In addition, clock division techniques can also be used to accommodate particular technical requirements. A common feature to these conventional implementations is a finite phase step ΔφLSB=1/N (UI) or quantizing effect in tracking the data phase.
When a frequency offset +/−fppm exists between the frequency of the received data signal and the frequency of a local reference, then the clock recovery circuit generates an associated jitter component in the recovered clock signal 310 as described earlier in connection with FIG. 2. One way to reduce this jitter component is to increase the number of phases N, which decreases the size of the associated phase quantizing step. However, as previously described, there exist practical limits, such as cost and/or physical constraints, to the use of relatively large values for N. For example, limiting factors can include: timing accuracy in generating and distributing a relatively large number of N phases, a frequency limit associated with the loop to operate the phase selection unit 308, and the like. Other disadvantages include an increase in die area, chip cost, and an increase in power. Jitter due to a frequency offset +/−fppm can be observed in prior art clock recovery systems.
FIG. 4 illustrates a conventional clock recovery system with an analog clock synthesis unit (analog CSU) 402. The analog CSU 402 is another conventional technique to reduce jitter in the recovered clock signal for a SONET system.
The bandwidth of an analog CSU 402 is typically set below 12 kHz to suppress the quantizing jitter from the digital clock recovery 404 for the SONET bandwidth as described earlier in connection with Table 1. An implementation of the analog CSU 402 is disadvantageously expensive and mechanically fragile because of the presence of a low-noise crystal oscillator 406 in the analog CSU 402. Other less expensive and less fragile oscillators, such as monolithic oscillators, exhibit relatively high intrinsic phase noise and are typically not satisfactory for filtering in a low-frequency band such as in an analog CSU 402.